New PDF release: Advances in Electronic Testing: Challenges and Methodologies

By Dimitris Gizopoulos

ISBN-10: 0387294082

ISBN-13: 9780387294087

ISBN-10: 0387294090

ISBN-13: 9780387294094

This is a brand new kind of edited quantity within the Frontiers in digital checking out booklet sequence dedicated to fresh advances in digital circuits trying out. The publication is a complete elaboration on vital issues which seize significant learn and improvement efforts this present day. "Hot" themes of present curiosity to check expertise neighborhood were chosen, and the authors are key individuals within the corresponding topics.

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Extra resources for Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)

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Capacitive Defects It has long been known that logic synthesis will result in additional near critical paths and hence additional delay faults [21]. As designs shrink, two additional issues come to the fore: capacitive defects and signal integrity effects. Let us look in more detail at the former. These have the property that they result in timing related failures at low operating frequency, but not high frequency. Originally, bridging faults were considered to have zero resistance. Later resistance models were added.

The physical motivation for these is shown in Figure 1-22. This type of behavior, which has been observed in silicon, although not in silicon that is within process specifications (at least to the author’s knowledge), shows that low speed tests are needed, in addition to full speed tests, to ensure high quality. 6 27 IDDQ Models In addition to conventional logic testing, where inputs are applied to a circuit and output responses are measured, circuits can be tested parametrically. One example of such a test is an IDDQ test (IDD is the drain current in a CMOS circuit, the “Q” refers to the quiescent or static state).

G. wide metal dishing on one layer can cause shorts in the layer above as wires fold in on each other). The fourth mechanism, scratches, result in combinations of shorts and opens, spread across relatively large areas [6]. Figure 1-6: Dishing and Erosion (courtesy Applied Materials). 4 In addition to CMP-induced defects, voids (also known as partial opens) are another major defect mechanism. These defects often have an easily recognizable signature: delay faults at low temperatures. This happens because of thermal expansion of the copper into the void.

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Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing) by Dimitris Gizopoulos

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